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struct { | |
| |
|
uint8_t BANK0 = 0U | |
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uint8_t BANK1 = 1U | |
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|
uint8_t BANK2 = 2U | |
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|
uint8_t BANK3 = 3U | |
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|
uint8_t BANK4 = 4U | |
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|
uint8_t BANK_MASK = 0b11111000 | |
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| } | BANK | |
| |
|
struct { | |
| |
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uint8_t ACCEL_LOW_NOISE = 0b1100 | |
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uint8_t GYRO_LOW_NOISE = 0b11 | |
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| } | PWR_MGMT0 | |
| |
|
struct { | |
| |
|
uint8_t FIFO_HOLD_LAST_DATA_EN = 0b10000000 | |
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|
uint8_t FIFO_HOLD_LAST_DATA_EN_MASK = 0b01111111 | |
| |
|
uint8_t FIFO_COUNT_REC_IN_COUNT = 0b01000000 | |
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|
uint8_t FIFO_COUNT_REC_IN_COUNT_MASK = 0b10111111 | |
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| } | INTF_CONFIG0 | |
| |
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struct { | |
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|
uint8_t RTC_ENABLE = 0b00001101 | |
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uint8_t RTC_MASK = 0b11110000 | |
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| } | INTF_CONFIG1 | |
| |
|
struct { | |
| |
|
uint8_t PIN9_CLKIN = 0b100 | |
| |
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uint8_t PIN9_FSYNC = 0b10 | |
| |
|
uint8_t PIN9_INT2 = 0 | |
| |
|
uint8_t PIN9_MASK = 0b11111001 | |
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| } | INTF_CONFIG5 | |
| |
|
struct { | |
| |
|
uint8_t _32kHz = 0b0001 | |
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uint8_t _16kHz = 0b0010 | |
| |
|
uint8_t _8kHz = 0b0011 | |
| |
|
uint8_t _4kHz = 0b0100 | |
| |
|
uint8_t _2kHz = 0b0101 | |
| |
|
uint8_t _1kHz = 0b0110 | |
| |
|
uint8_t _500Hz = 0b1111 | |
| |
|
uint8_t _200Hz = 0b0111 | |
| |
|
uint8_t _100Hz = 0b1000 | |
| |
|
uint8_t _50Hz = 0b1001 | |
| |
|
uint8_t _25Hz = 0b1010 | |
| |
|
uint8_t _12_5Hz = 0b1011 | |
| |
| } | GYRO_ODR | |
| |
|
struct { | |
| |
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uint8_t _2000dps = 0b000 | |
| |
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uint8_t _1000dps = 0b001 | |
| |
|
uint8_t _500dps = 0b010 | |
| |
|
uint8_t _250dps = 0b011 | |
| |
|
uint8_t _125dps = 0b100 | |
| |
|
uint8_t _62_5dps = 0b101 | |
| |
|
uint8_t _31_25dps = 0b110 | |
| |
|
uint8_t _15_625dps = 0b111 | |
| |
| } | GYRO_RANGE | |
| |
|
struct { | |
| |
|
uint8_t _32kHz = 0b0001 | |
| |
|
uint8_t _16kHz = 0b0010 | |
| |
|
uint8_t _8kHz = 0b0011 | |
| |
|
uint8_t _4kHz = 0b0100 | |
| |
|
uint8_t _2kHz = 0b0101 | |
| |
|
uint8_t _1kHz = 0b0110 | |
| |
|
uint8_t _500Hz = 0b1111 | |
| |
|
uint8_t _200Hz = 0b0111 | |
| |
|
uint8_t _100Hz = 0b1000 | |
| |
|
uint8_t _50Hz = 0b1001 | |
| |
|
uint8_t _25Hz = 0b1010 | |
| |
|
uint8_t _12_5Hz = 0b1011 | |
| |
| } | ACC_ODR | |
| |
|
struct { | |
| |
|
uint8_t _16g = 0b000 | |
| |
|
uint8_t _8g = 0b001 | |
| |
|
uint8_t _4g = 0b010 | |
| |
|
uint8_t _2g = 0b011 | |
| |
| } | ACC_RANGE | |
| |
|
struct { | |
| |
|
uint8_t _4000HZ = 0b000 | |
| |
|
uint8_t _170HZ = 0b001 | |
| |
|
uint8_t _82HZ = 0b010 | |
| |
|
uint8_t _40HZ = 0b011 | |
| |
|
uint8_t _20HZ = 0b100 | |
| |
|
uint8_t _10HZ = 0b101 | |
| |
|
uint8_t _5HZ = 0b111 | |
| |
|
uint8_t TEMP_FILT_BW_MASK = 0b00011111 | |
| |
| } | TEMP_FILT_BW | |
| |
|
struct { | |
| |
|
uint8_t ODR_DIV_2 = 0 | |
| |
|
uint8_t ODR_DIV_4 = 1 | |
| |
|
uint8_t ODR_DIV_5 = 2 | |
| |
|
uint8_t ODR_DIV_8 = 3 | |
| |
|
uint8_t ODR_DIV_10 = 4 | |
| |
|
uint8_t ODR_DIV_16 = 5 | |
| |
|
uint8_t ODR_DIV_20 = 6 | |
| |
|
uint8_t ODR_DIV_40 = 7 | |
| |
|
uint8_t LOW_LATENCY_ODR = 14 | |
| |
|
uint8_t LOW_LATENCY_8_ODR = 15 | |
| |
| } | ACC_GYRO_FILTER_BW | |
| |
|
struct { | |
| |
|
uint8_t _1st_ORDER = 0 | |
| |
|
uint8_t _2nd_ORDER = 1 | |
| |
|
uint8_t _3rd_ORDER = 2 | |
| |
|
uint8_t _DISABLED = 3 | |
| |
|
uint8_t GYRO_MASK = 0b11110011 | |
| |
|
uint8_t ACC_MASK = 0b11100111 | |
| |
| } | ACC_GYRO_FILTER_ORDER | |
| |
|
struct { | |
| |
|
uint8_t HIGH_RES_FULL_FIFO_PACKET_4 = 0b10111 | |
| |
|
uint8_t FIFO_PACKET_3 = 0b00111 | |
| |
|
uint8_t FIFO_PACKET_MASK = 0b10000000 | |
| |
| } | FIFO_CONFIG1 | |
| |
|
struct { | |
| |
|
uint8_t STREAM_2_FIFO = 0b01000000 | |
| |
|
uint8_t FIFO_MODE_MASK = 0b00111111 | |
| |
| } | FIFO_CONFIG | |
| |
|
struct { | |
| |
|
uint8_t FIFO_FLUSH_TRUE = 0b00000010 | |
| |
|
uint8_t FIFO_FLUSH_MASK = 0b11111101 | |
| |
| } | SIGNAL_PATH_RESET | |
| |
|
struct { | |
| |
|
uint8_t WOM_INT_MODE_OR = 0b00000000 | |
| |
|
uint8_t WOM_INT_MODE_AND = 0b00001000 | |
| |
|
uint8_t WOM_INT_MODE_MASK = 0b11110111 | |
| |
|
uint8_t WOM_MODE_ABS = 0b00000000 | |
| |
|
uint8_t WOM_MODE_DELTA = 0b00000100 | |
| |
|
uint8_t WOM_MODE_MASK = 0b11111011 | |
| |
|
uint8_t SMD_MODE_DISABLED = 0b00000000 | |
| |
|
uint8_t SMD_MODE_RESERVED = 0b00000001 | |
| |
|
uint8_t SMD_MODE_SHORT = 0b00000010 | |
| |
|
uint8_t SMD_MODE_LONG = 0b00000011 | |
| |
|
uint8_t SMD_MODE_MASK = 0b11111100 | |
| |
| } | APEX_WOM_CONF | |
| |
|
struct { | |
| |
|
uint8_t WOM_TO_INT1_EN = 0b00000111 | |
| |
|
uint8_t WOM_TO_INT1_DIS = 0b00000000 | |
| |
|
uint8_t WOM_TO_INT1_MASK = 0b11111000 | |
| |
|
uint8_t SMD_TO_INT1_EN = 0b00001000 | |
| |
|
uint8_t SMD_TO_INT1_DIS = 0b00000000 | |
| |
|
uint8_t SMD_TO_INT1_MASK = 0b11110111 | |
| |
| } | INT_SOURCE1 | |
| |
|
struct { | |
| |
|
uint8_t INT1_POLARITY_ACTIVE_LOW = 0b00000000 | |
| |
|
uint8_t INT1_POLARITY_ACTIVE_HIGH = 0b00000001 | |
| |
|
uint8_t INT1_POLARITY_MASK = 0b11111110 | |
| |
|
uint8_t INT1_DRIVE_OPEN_DRAIN = 0b00000000 | |
| |
|
uint8_t INT1_DRIVE_PUSH_PULL = 0b00000010 | |
| |
|
uint8_t INT1_DRIVE_MASK = 0b11111101 | |
| |
|
uint8_t INT1_MODE_PULSED = 0b00000000 | |
| |
|
uint8_t INT1_MODE_LATCHED = 0b00000100 | |
| |
|
uint8_t INT1_MODE_MASK = 0b11111011 | |
| |
|
uint8_t INT1_CONF_MASK = 0b11111000 | |
| |
| } | INT_CONFIG | |
| |
|
struct { | |
| |
|
uint8_t INT_ASYNC_RESET = 0b00000000 | |
| |
|
uint8_t INT_ASYNC_MASK = 0b11101111 | |
| |
| } | INT_CONFIG1 | |
| |
1.9.8